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ADT7473
For applications where the monitoring cycle time is
important, it can easily be calculated. The total number of
channels measured is:
? One Dedicated Supply Voltage Input (V CCP )
? Supply Voltage (V CC Pin)
? Local Temperature
Table 27. INTERRUPT STATUS REGISTER 1
(REG. 0X41)
Bit Mnemonic Description
7 OOL 1 denotes a bit in Interrupt Status
Register 2 is set and Interrupt Status
Register 2 should be read.
? Two Remote Temperatures
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature
monitoring with averaging disabled is 19 ms. The ADT7473/
ADT7473 ? 1 is a derivative of the ADT7467. As a result, the
total conversion time in the ADT7473/ ADT7473 ? 1 is the
same as the total conversion time of the ADT7467, even
though the ADT7473/ADT7473 ? 1 has fewer monitored
channels.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
6
5
4
3
2
1
0
R2T
LT
R1T
?
V CC
V CCP
?
1 indicates that the Remote 2
Temperature High or Low Limit has
been exceeded.
1 indicates that the Local Temperature
High or Low Limit has been exceeded.
1 indicates that the Remote 1
Temperature High or Low Limit has
been exceeded.
Unused
1 indicates that the V CC High or Low
Limit has been exceeded.
1 indicates that the V CCP High or Low
Limit has been exceeded.
Unused
Interrupt Status Registers
The results of limit comparisons are stored in Interrupt
Table 28. INTERRUPT STATUS REGISTER 2
(REG. 0X42)
Status Register 1 and Interrupt Status Register 2. The status
register bit for each channel reflects the status of the last
measurement and limit comparison on that channel. If a
measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out of limits,
the corresponding status register bit is set to 1.
The state of the various measurement channels can be
polled by reading the status registers over the serial bus. In
Bit 7 (OOL) of Interrupt Status Register 1 (Reg. 0x41), a 1
means an out-of-limit event has been flagged in Interrupt
Status Register 2. This means the user needs only to read
Interrupt Status Register 2 when this bit is set. Alternatively,
Pin 5 or Pin 9 on the ADT7473 can be configured as an
SMBALERT output, while only Pin 9 can be configured to
be an SMBALERT on the ADT7473 ? 1. This automatically
notifies the system supervisor of an out-of-limit condition.
Reading the status registers clears the appropriate status bit
as long as the error condition that caused the interrupt has
cleared. Status register bits (except OVT) are sticky.
Whenever a status bit is set, indicating an out-of-limit
Bit
7
6
5
4
3
2
1
0
Mnemonic
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
THERM
Limit Latch
Description
1 indicates an open or short on
D2+/D2 ? inputs.
1 indicates an open or short on
D1+/D1 ? inputs.
1 indicates that Fan 4 has dropped
below the minimum speed. Alternatively,
indicates that THERM timer limit has
been exceeded if the THERM timer
function is used.
1 indicates that Fan 3 has dropped
below the minimum speed.
1 indicates that Fan 2 has dropped
below the minimum speed.
1 indicates that Fan 1 has dropped
below the minimum speed.
1 indicates that a THERM
overtemperature limit has been
exceeded.
1 indicates that a Remote Channel 2
latch.
condition, it remains set even if the event that caused it has
gone away (until read). The only way to clear the status bit
is to read the status register after the event has gone away.
Interrupt mask registers (Register 0x74 and Register 0x75)
allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is
SMBALERT Interrupt Behavior
The ADT747/ADT7473 ? 1 can be polled for status, or an
SMBALERT interrupt can be generated for out-of-limit
conditions. It is important to note how the SMBALERT
output and status bits behave when writing interrupt handler
software.
set in the interrupt status registers. OVT clears
automatically.
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